Makefile include env file

environment-variablesmake

I'm trying to include some env vars into a Makefile. The env file looks like:

FOO=bar
BAZ=quux

Note there's no leading export to each env var. If I add the leading export and just include the env file in the Makefile, everything works as it should. But I need to keep the env vars sans leading export. That prevents me from just using include envfile in the Makefile.

I've also tried doing something like this:

sed '/^#/!s/^/export /' envfile > $(BUILDDIR)/env
include $(BUILDDIR)/env

But doing that cause make to throw an error because the env file isn't there for including.

Best Answer

If you are using gnu make, what should work is to include the envfile file, then export the list of vars got from the same file:

#!make
include envfile
export $(shell sed 's/=.*//' envfile)

test:
        env

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Adding directory to PATH through Makefile

You simply can't do this. There's no way¹ the make process can change its parent's environment (or its current directory, which you might be thinking of next).

In fact, even less is happending than you think.

Not all make implementations reflect the assignment to the make PATH variable in the environment; GNU make (found on Linux and other systems) does, but BSD make doesn't.
Each command line under a target runs in a separate subshell. (Except in some older BSD make implementations.) So the export PATH line is running on a shell that terminates immediately afterwards. Not that this line would be doing anything in the first place — if PATH is defined at that point, it's because it's in the shell's environment already.

Make is for building things automatically. If you want to set variables for your interactive environment, this isn't the tool you should be looking at. Instead, write a shell snippet, and source it in the current shell:

. ./define-my-variables.sh

In your makefile, source the script in every subshell. You can use a backslash to make a long command; remember that

The backslash-newline sequence is stripped by make, so the shell won't see a newline there.
Remember to prefix each line by a tab nonetheless.
Make's error behavior is to abort if a command fails. The shell won't do that by default, and the failure of any command but the last will go unnoticed by default, so you need to run set -e.

install:
    set -e; \
    . ./define-my-variables.sh; \
    mkdir -p bin; \
    …

¹ _{Obligatory note: no sane way. Even remotely invoking chdir via ptrace from a debugger won't work as is with most shells because they don't like to have their current directory changed under their feet.}

Bash – How to Iterate Bash Associative Array in Makefile

If your code excerpt is properly representative, it seems that you are typing Bash commands directly in your Makefile and expecting Make to execute them with Bash. That's not how it works. The syntax of a Makefile is entirely different. Within a recipe, you can type Bash commands; each separate line in a recipe will be executed in a separate sub-shell. So you need at least two changes:

Your shell commands need to be in a target.
The declare needs to run in the same shell as the loop; otherwise you declare in one Bash instance, then exit that, then run the loop in a separate instance which knows nothing about the now-lost declare.

Here is a simple refactoring of your Makefile with these changes.

SHELL=/bin/bash   # This is the standard compliant method

.PHONY: all
all:
    declare -A PROVS=( ["NL"]=10 ["PE"]=11 ["NS"]=12 ["NB"]=13 \
        ["QC"]=24 ["ON"]=35 ["MB"]=46 ["SK"]=47 ["AB"]=48 \
        ["BC"]=59 ["YK"]=60 ["NT"]=61 ["NU"]=62 )\
    ; for key in "$${!PROVS[@]}" ; do \
        touch "foo_$${key}_$${PROVS[$${key}]}" ; \
    done

Demo: http://ideone.com/t94AOB

The @ convention to run a command silently applies to the entire command line. Thus, you can put it before declare above, in which case it will be stripped off before the entire command line is submitted to Bash. Anywhere else, it will not be stripped or understood, and it will obviously cause a Bash syntax error in the called shell.

(The obsession with @ rules is an anti-pattern anyway. Run with make -s if you don't want to see the output; shutting up make will only make it harder to debug your rules.)

Best Answer

Related Solutions

Adding directory to PATH through Makefile

Bash – How to Iterate Bash Associative Array in Makefile

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