How to list all targets in make

That behaviour is not a bug. It is a feature. A feature and a possible user error to be precise.

The feature in question is one of the implicit rules of Make. In your case the implicit rule to "build" *.sh files. The user error, your error, is not changing the working directory before invoking the makefile in the subdirectories.

TL; DR: to fix this you can do one or more of the following:

1. Fix the shell script to change the working directory:

   #!/bin/bash
   
   for f in *; do
           if [[ -d $f && -f $f/makefile ]]; then
                   echo "Making clean in $f..."
                   (cd $f; make clean)
           fi
   done
   

2. Make the empty rules explicit:

   clean: ;
   

3. Make the clean targets phony:

   .PHONY: clean
   

Detailed explanation:

Make has a bunch of implicit rules. This allows one to invoke make on simple projects without even writing a makefile.

Try this for a demonstration:

1. create an empty directory and change in to the directory
2. create a file named clean.sh.
3. run make clean

Output:

$ make clean
cat clean.sh >clean 
chmod a+x clean

BAM! That is the power of implict rules of make. See the make manual about implicit rules for more information.

I will try to answer the remaining open question:

Why does it not invoke the implicit rule for the first makefile? Because you overwrote the implicit rule with your explicit clean rule.

Why does the clean rule in the second makefile not overwrite the implicit rule? Because it had no recipe. Rules with no recipe do not overwrite the implicit rules, instead they just append prerequisites. See the make manual about multiple rules for more information. See also the make manual about rules with explicit empty recipes.

Why is it an error to not change the working directory before invoking a makefile in a subdirectory? Because make does not change the working directory. Make will work in the inherited working directory. Well technically this is not necessarily an error, but most of the time it is. Do you want the makefiles in the subdirectories to work in the subdirectories? Or do you want them to work in the parent directory?

Why does make ignore the explicit clean rule from the first makefile in the second invocation of clean.sh? Because now the target file clean already exists. Since the rule clean has no prerequisites there is no need to rebuild the target. See the make manual about phony targets which describes exactly this problem.

Why does make search for the target three/makefile in the third invocation? Because make always tries to remake the makefiles before doing anything else. This is especially true if the makefile is explicitly requested using -f but it does not exists. See the make manual about remaking makefiles for more information.

The bash-completion package doesn't do this, it does some acrobatics to handle both command line options and extract a list of Makefile targets, but it does not try to generate matches by applying wildcards or otherwise handling any pattern rules.

It can be done however, here's a simple version with a few caveats.

function _mkcache() {
    local _file="$1"
    # add "-r" to omit defaults (60+ rules)
    ${MAKE:-make} ${_file:+-f "$_file"} -qp 2>/dev/null |
    gawk '/^# *Make data base/,/^# *Finished Make data base/{
      if (/^# Not a target/) { getline; next }
      ## handle "target: ..."
      if (match($0,/^([^.#% ][^:%=]+) *:($|[^=])(.*)/,bits)) {
          #if (bits[3]=="") next # OPT: skip phony
          printf("%s\n",bits[1])
      }
      ## handle "%.x [...]: %.y [| x]", split into distinct targets/prereqs
      else if (match($0,/^([^:]*%[^:]*) *(::?) *(.*%.*) *(\| *(.*))?/,bits)) {
          #if (bits[3]=="%") next # OPT: skip wildcard ones
          nb1=split(bits[1],bb1)
          nb3=split(bits[3],bb3)
          for (nn=1; nn<=nb1; nn++) 
            for (mm=1; mm<=nb3; mm++) 
              printf("%s : %s\n",bb1[nn],bb3[mm])
      }
      ## handle fixed (no %) deps
      else if (match($0,/^([^:]*%[^:]*) *(::?) *([^%]*)$/,bits)) {
          if (bits[3]=="") next # phony
          printf("%s : %s\n",bits[1],bits[3])
      }
      ## handle old form ".c.o:"  rewrite to new form "%.o: %.c"
      else if (match($0,/^\.([^.]+)\.([^.]+): *(.*)/,bits)) {
          printf("%%.%s : %%.%s\n", bits[2],bits[1])
      }
    }' > ".${_file:-Makefile}.targets"
}

function _bc_make() {
    local ctok=${COMP_WORDS[COMP_CWORD]}   # curr token
    local ptok=${COMP_WORDS[COMP_CWORD-1]} # prev token
    local -a mkrule maybe
    local try rr lhs rhs rdir pat makefile=Makefile

    ## check we're not doing any make options 
    [[ ${ctok:0:1} != "-" && ! $ptok =~ ^-[fCIjloW] ]] && {
        COMPREPLY=()
        [[ "$makefile" -nt .${makefile}.targets ]] && 
            _mkcache "$makefile"

        mapfile -t mkrule < ".${makefile}.targets"
        # mkrule+=( "%.o : %.c" )  # stuff in extra rules

        for rr in "${mkrule[@]}"; do
            IFS=": " read lhs rhs <<< $rr

            ## special "archive(member):"
            [[ "$lhs" =~ ^(.*)?\((.+)\) ]] && {
                continue # not handled
            }

            ## handle simple targets
            [[ "$rhs" == "" ]] && {
                COMPREPLY+=( $(compgen -W "$lhs" -- "$ctok" ) )
                continue
            }

            ## rules with a path, like "% : RCS/%,v" 
            rdir=""
            [[ "$rhs" == */* ]] && rdir="${rhs/%\/*/}/" 
            rhs=${rhs/#*\//}

            ## expand (glob) that matches RHS 
            ## if current token already ends in a "." strip it
            ## match by replacing "%" stem with "*"

            [[ $ctok == *. ]] && try="${rdir}${rhs/\%./$ctok*}" \
                              || try="${rdir}${rhs/\%/$ctok*}"

            maybe=( $(compgen -G "$try") )  # try must be quoted

            ## maybe[] is an array of filenames from expanded prereq globs
            (( ${#maybe[*]} )) && {

               [[ "$rhs" =~ % ]] && {
                   ## promote rhs glob to a regex: % -> (.*)
                   rhs="${rhs/./\\.}"
                   pat="${rdir}${rhs/\%/(.*)}"

                   ## use regex to extract stem from RHS, sub "%" on LHS
                   for nn in "${maybe[@]}"; do 
                       [[ $nn =~ $pat ]] && {
                           COMPREPLY+=( "${lhs/\%/${BASH_REMATCH[1]}}" )
                       }
                   done
               } || {
                   # fixed prereqs (no % on RHS)
                   COMPREPLY+=( "${lhs/\%/$ctok}" )   
               }
            }
        done
        return
    }
    COMPREPLY=() #default
}
complete -F _bc_make ${MAKE:-make}

There are two parts, a function _mkcache extracts all the rules and targets from a Makefile and caches these. It also does a bit of processing so the rules are simplified to a single "target : pre-req" form in that cache.

Then, a completion function _bc_make takes the token you attempt completion on and tries to match against targets, and uses the pattern rules to expand a glob based on the pre-requisites and the word for completion. If one or more matches are found, it builds a list of targets based on the pattern rules.

GNU make is assumed. It should correctly handle:

• targets and pattern rules (though not all of them, see below)
• new and old form .c.o → %.o : %.c
• paths in prereqs (e.g RCS/)
• with or without all default rules (add -r to make if preferred)

Caveats, and not supported:

• intermediate or chained dependencies, it's not as smart as make
• VPATH or vpath
• .SUFFIXES
• make -C dir
• "archive(member)" targets, explicit or implicit
• make options expansion
• pathological junk in the environment that can cause Makefile parsing problems (TERMCAP for example)
• Makefiles named other than Makefile

Some of the above can be added relatively simply, others like archive handling are not so simple.