The man for cpuset doesn't seem to clearly list how to figure out which numbers map to which processing units. My current machine has two Intel Xeon E5645s, each of which has 6 cores and hyperthreading enabled, so I have 24 total processing units I can refer to with cpusets. My challenges are 1) determine which cpuset ID numbers map to which processor 2) determine which cpuset id numbers are paired (e.g. siblings on a core)
Are the numbers that lscpu outputs the same identifiers I should use to refer to cpu set processors? If so, it seems the numbers are alternated here, and this answers (1) with "evens are one processor, odds are the other processor", but I'm not sure if I'm reading it correctly.
$ lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 24
On-line CPU(s) list: 0-23
Thread(s) per core: 2
Core(s) per socket: 6
Socket(s): 2
NUMA node(s): 2
Vendor ID: GenuineIntel
CPU family: 6
Model: 44
Stepping: 2
CPU MHz: 2393.964
BogoMIPS: 4788.01
Virtualization: VT-x
L1d cache: 32K
L1i cache: 32K
L2 cache: 256K
L3 cache: 12288K
NUMA node0 CPU(s): 0,2,4,6,8,10,12,14,16,18,20,22
NUMA node1 CPU(s): 1,3,5,7,9,11,13,15,17,19,21,23
lstopo from the hwloc package seems to show me the answer to (2), and if I'm reading the man page correctly the P#... bits are the identifier "used by the OS", which leads me to believe these are the ones I need to pass to cpu sets. So limiting a process to cpus 0 and 12 would be allowing use of two threads on the same core, while limiting it to cpus 0 and 2 would be two threads on two different cores. Does that seem correct?
$ lstopo
Machine (35GB)
NUMANode L#0 (P#0 18GB) + Socket L#0 + L3 L#0 (12MB)
L2 L#0 (256KB) + L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0
PU L#0 (P#0)
PU L#1 (P#12)
L2 L#1 (256KB) + L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1
PU L#2 (P#2)
PU L#3 (P#14)
L2 L#2 (256KB) + L1d L#2 (32KB) + L1i L#2 (32KB) + Core L#2
PU L#4 (P#4)
PU L#5 (P#16)
L2 L#3 (256KB) + L1d L#3 (32KB) + L1i L#3 (32KB) + Core L#3
PU L#6 (P#6)
PU L#7 (P#18)
L2 L#4 (256KB) + L1d L#4 (32KB) + L1i L#4 (32KB) + Core L#4
PU L#8 (P#8)
PU L#9 (P#20)
L2 L#5 (256KB) + L1d L#5 (32KB) + L1i L#5 (32KB) + Core L#5
PU L#10 (P#10)
PU L#11 (P#22)
NUMANode L#1 (P#1 18GB) + Socket L#1 + L3 L#1 (12MB)
L2 L#6 (256KB) + L1d L#6 (32KB) + L1i L#6 (32KB) + Core L#6
PU L#12 (P#1)
PU L#13 (P#13)
L2 L#7 (256KB) + L1d L#7 (32KB) + L1i L#7 (32KB) + Core L#7
PU L#14 (P#3)
PU L#15 (P#15)
L2 L#8 (256KB) + L1d L#8 (32KB) + L1i L#8 (32KB) + Core L#8
PU L#16 (P#5)
PU L#17 (P#17)
L2 L#9 (256KB) + L1d L#9 (32KB) + L1i L#9 (32KB) + Core L#9
PU L#18 (P#7)
PU L#19 (P#19)
L2 L#10 (256KB) + L1d L#10 (32KB) + L1i L#10 (32KB) + Core L#10
PU L#20 (P#9)
PU L#21 (P#21)
L2 L#11 (256KB) + L1d L#11 (32KB) + L1i L#11 (32KB) + Core L#11
PU L#22 (P#11)
PU L#23 (P#23)
HostBridge L#0
PCIBridge
PCI 14e4:163a
Net L#0 "eth0"
PCI 14e4:163a
Net L#1 "eth1"
PCIBridge
PCI 102b:0532
PCI 8086:2921
Block L#2 "sda"
PCI 8086:2926
Best Answer
use
there you will get each hyperthread listed like this:
"processor" stands for the "logical processor", what is presented to the operating system as a processor. If you have hyper threading switched on, you will see two "logical processors" per core. The "physical id" will be the processor that you can touch (you have two of them).
Here is a listing from my 1-processor 4-core system with hyperthreading: