What NVME speeds should I expect from this motherboard’s PCIe slots

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I am testing this board: Gigabyte B550M DS3H > pdf manual

It has two M.2 slots and I want to also use two PCI-e connectors with adapters to add 2 more NVME drives (so 4 in total). It is for a MySQL db server, spreading read/write load.

I am confused about all the PCIe speeds because of the 3/4 version and x1, x2, x4 and so on.

Let's asume the actual NVME drives are fast, PCIe 4 running at 8GB/s.

  • First M.2 slot says PCIe 4.0 x4 so it means 8 GB/s ?
  • Second M.2 slot says PCIe 3.0 x2 so that is only 2GB/s ?
  • 1 x PCI Express x16 slot (PCIEX16) [...] support PCIe 4.0 x16 mode (main GPU connector), how many GB/s is that ?
  • 1 x PCI Express x16 slot (PCIEX4) [...] Supporting PCIe 3.0 x4 mode that is 4GB/s, correct ?

So I am trying to use the two wide PCI connectors to connect NVME drives using 16x PCIe NVME adapters.

For a video card I plan to plug a basic one with x1 connector in the remaining slot in the middle.

What are the maximum speeds for above ports ? And anything else that could go wrong with this ?

A second question … will 2 very fast NVME (e.g 8GB/s) perform better both connected in same one 4GB pci port than each NVME connected to two separate but slower 2GB/s pci ports ? (By "two in one port" I mean using a NVME adapter with two NVME slots). Can they slow one another if on same motherboard PCI slot ?

Best Answer

The Gigabyte B550M DS3H (rev. 1.x) has the information that was asked:

enter image description here

The PCIe 4.0 x16 port can theoretically deliver up to 31.5 GB/s, while the PCIe 3.0 x16 can do up to 15.8 GB/s.

You will find below the theoretical limit of all ports together (again, very theoretically):

enter image description here

While Gigabyte boasts that theoretically this design delivers up to 64 Gb/s data transfer speed, it should be remembered that when launched, this was the cheapest and the lowest-level motherboard in the B550 product stack.

It's also normal for the highest-performance ports to have lane priority over the others, so devices connected to lower-performance ports, when the higher-performance ports are active, may perform at a fraction of their speed (this can be as low as one-half and one-fourth - example).

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