That above is a nice pic. From the P4 days, so a bit old, but simple and clear. I have included a more modern one too but this one helps understand the basic structure a bit more since there's less on it, and it's good to have a few pics, and you rightly wanted a few.
Nothing on there looks very strange to me, it looks as I remember from previous pictures i've seen!
You see the processor/CPU. Then you see 2 squares. The one near the CPU is called the northbridge. The one below it is called the southbridge.
To answer your questions
"I am getting confused among various buses like local bus,PCI bus, SCSI bus,ISA bus,USB bus. I am looking for block diagrams. How is the USB port connected to processor ultimately? through PCI bus etc? Why do we have so many buses? What was it like before SCSI/IDE came?..." "vaughn diagram It shows no connection between PCI bus and SCSI bus. Is that correct?".. "If disks connected through SCSI interface are anyway in turn go to PCI bus, then speed would be limited by PCI bus then why not connect these disks directly to PCI bus. Why is SCSI bus needed in the first place?"
"local bus" , the term you use, might not mean anything.
The bus connecting the CPU to the northbridge, is I think called the FSB (front side bus)
ISA is way too old, not on this pic(And this is an old pic P4 is old). ISA was replaced by PCI long long ago. Even 15 years ago ISA was probably going out.. it has been finished for years.. you won't see it now.
SCSI is not on this diagram. It was common in servers.. http://en.wikipedia.org/wiki/SCSI says that with the advent of SATA, SCSI is being discontinued. I suppose IDE/(P)ATA had weaknesses that SCSI didn't.
AGP is connected to the northbridge. Though AGP is old. I guess that line in the diagram is the AGP bus
RAM is connected to the northbridge. I suppose that "line" connecting it is called the memory bus.
ATA is on the southbridge. IDE is a colloquial even amongst techies, way of referring to PATA/P-ATA. People started calling IDE "PATA" instead of just ATA, once SATA came out.
PCI is on the southbridge.
LAN is on the southbridge.
Really there isn't a lot connected to the northbridge, other than RAM. THere was AGP but it is old. Now though there is PCIe..
PCIe i'm not sure it may be possible for it to be on either.. see this pic
http://www.pcstats.com/articleimages/200801/foxdigtalifeX38a_X38Block.gif
Chipset designs do vary, so it's worth looking for a few diagrams and trying to see if there are similarities. But I think you may find that anything with a northbridge and southbridge follows that pattern.
Added
The following is based on something that superuser user 'Shivendra' wished to mention - Northbridge is a faster chip, than the southbridge, and is an intermediary connecting faster components - RAM, AGP(though AGP is old now), and PCIe, to the CPU. The Southbridge has LAN, USB, PCI(though PCI is old now).link link link
And in fact, that design with northbridge and southbridge was called the Intel Hub Architecture, but was phased out. I'm no expert, but it was replaced with a new design that instead of the 2 chips - northbridge and southbridge, had integrated much northbridge functionality into the CPU, and besides the CPU, has just one chip, the PCH which has some functionality of what was the northbridge, and functionality of what was the southbridge. In that more modern architecture, RAM connects directly with the CPU. (directly - no intermediary), so, instead of to the northbridge that it had before. The modern architecture has a memory controller built into the CPU.
The short answer is "Yes", if the BIOS (which performs initial enumeration) adheres to PCI specification.
According to:
"PCI Express System Architecture" R. Budruk, D. Anderson, T. Shanley, ADDISON-WESLEY DEVELOPER´S PRESS, 2003. ISBN: 0-321-15630-7, page 743:
The specification states that the enumeration software must perform a
depth-first search, so before proceeding to discover additional functions/
devices on bus 0, it must proceed to search bus 1.
And for RHEL 6:
9. Devices and Device Drivers
PCI Device Ordering
In Red Hat Enterprise Linux 6, the PCI device ordering is based on the PCI device
enumeration. PCI device enumeration is based on the PCI enumeration algorithm (depth
first then breadth) and is constant per system type. Additionally, once the devices are
discovered, the module loading process is sequentialized, providing persistent naming of
the interfaces.
However, (some versions of?) Linux support a kernel parameter "pci=bfsort" which changes the Linux enumeration algorithm to "breadth first". This will change the order that the Linux kernel loads and initialises PCI devices wrt how BIOS does.
In any case, from boot-to-boot, enumerated lists will still contain detected items in the same order.
Best Answer
The device is determined by a hardware line IDSEL that is an input to every PCI endpoint. During configuration transactions, the IDSEL is used to indicate to a PCI endpoint (or bridge) that it is currently selected. In terms of determining the actual device number, this is done by the host hardware. If for example a motherboard has two PCI endpoint slots, there will be two discrete IDSEL lines from the CPU to the endpoints. This is seen in the picture below:
Additionally, it seems that in practice, it is common to tie these IDSEL lines to a one hot mapping from the 32 bit address/data bus. When a configuration is taking place, the address line will assert a one hot address such as 0x00000010. The one bit of the address/data bus will be brought in as the IDSEL for a particular endpoint. Since there are 32 possible devices per bus, this works out nicely. As an example of this, assume that there is a motherboard with 5 possible devices. The following could be an example mapping.