How can RAM contain a “memory map” if RAM is unaware of the overall system

Ah, this is one of those simple questions that have really complex answers. The simple answer is, well, it depends on how the write was done and what sort of caching there is. Here's a useful primer on how caches work.

CPUs can write data in various ways. Without any caching, the data is stored in memory straightaway and the CPU waits for the write to complete. With caching, the CPU usually stores data in program order, i.e. if the program writes to address A then address B then the memory A will be written to before memory B, regardless of the caching. The caching only affects when the physical memory is updated, and this depends on the type of caching used (see the above link). Some CPUs can also store data non-temporally, that is, the writes can be re-ordered to make the most of memory bandwidth. So, writing to A, then B, then (A+1) could be reorderd to writing to A then A+1 in a single burst, then B.

Another complication is when more than one CPU is present. Depending on the way the system is designed, writes by one CPU won't be seen by other CPUs because the data is still in the first CPUs cache (the cache is dirty). In multiple CPU systems, making each CPU's cache match what is in physical memory is termed cache consistancy. There are various ways this can be acheived.

Of course, the above is geared towards Pentium processors. Other processors can do things in other ways. Take, for example, the PS3's Cell processor. The basic architecture of a Cell CPU is one PowerPC core with several Cell cores (on the PS3 there are eight cells one of which is always disabled to improve yields). Each cell has its own local memory, sort of an L1 cache which is never written to system RAM. Data can be transferred between this local RAM and system RAM using DMA (Direct Memory Access) transfers. The cell can access system RAM and the RAM of other cells using what appears to be normal reads and writes but this just triggers a DMA transfer (so it's slow and really should be avoided). The idea behind this system is that the game is not just one program, but many smaller programs that combine to do the same thing (if you know *nix then it's like piping command line programs to achieve more complex tasks).

To sum up, writing to RAM used to be really simple in the days when CPU speed matched RAM speed, but as CPU speed increased and caches were introduced, the process became more complex with many different methods.

Skizz

The physical address space is huge nowadays due to 64 bit addressing. Many devices, for example AHCI-compliant disk controllers, require quite big chunks of address space to be mapped to the device registers.

Also, the IO address space is not accessible with usual assembler instructions. It is accessible only with special instructions that can read from and write to the IO ports. This is not really convenient and inefficient in many cases.

For example the above mentioned ACPI compliant controller has some functionality that requires the processor to execute locked read-modify-write operation to change a single bit in a device register provided no other cores will be able access and modify the same register in between. With IO address space this is not possible at all.

One more point we should take to account is that the PCI bus is not unique to the x86 architecture. There are other architectures exist that has no special IO bus at all. So the device vendors prefer not to use IO addresses to stay compatible with most systems. Thus no one is using the IO address space. Then why not make de-jure the thing that is de-facto for a long time already?