CPU-Z say the SPD RANK number is “dual” and “single?”

DIMM slots of the same colour indicate different channels. In the figure, DIMM1 and DIMM3 are on channel A, whereas DIMM2 and DIMM4 are on channel B. In order to make use of dual-channel operation, both channels should have a RAM module with matching capacity, hence the manual suggests installing two matching-capacity modules into DIMM1 and DIMM2. (DIMM1 and DIMM2, as well as DIMM3 and DIMM4, seem to be paired, so you cannot install matching size modules into DIMM1 and DIMM4, for instance, despite them technically being on different channels as well.) Extra, unpaired RAM modules will run in single-channel mode, no matter their capacity. In the example, that means 4 GiB dual channel RAM from the 2+2 configuration plus 4 GiB of single channel RAM from the single 4 GiB RAM module.

In other words, the 4 GiB size of the other module is just for illustration that the sizes need not match in that case. That 2 GiB + 2 GiB = 4 GiB is a coincidence. The following figure also shows a 2+2 & 4+4 configuration in dual channel, illustrating that the paired slots will continue to run in dual channel mode as long as the capacities across channels match (thus it's 6 GiB per channel in dual-channel configuration).

That's Correct. This specific naming convention is as follows(each vendor differs slightly):

[32GB][8Gb][x4][DR]

[DIMM_TOTAL_SIZE(in gigabytes)] [DRAM SIZE(in gigabits)] [number of data bits per dram (column width)] [number of ranks]

32GB = (8 * 16 * 2) / 8

8 gigabits * 16 chips (drams) per rank * 2 ranks = 256 gigabits

256 gigabits / 8 = 32 gigabytes.

The number of bank resource a DRAM contains (density) is internal to the DRAM and not consequential here. It is factored into [DRAM SIZE(in gigabits)].

For different DRAM width of the same density:

a x4 will contain twice the number of bank resources of that of a x8

a x8 will contain twice the number of bank resources of that of a x16

there is a performance advantage to having more bank resources per dram, since a dram can only have one page (or row) open per bank at any given time. In general, a x4 will perform better than a x8, which will perform better than a x16 (all other factors being equal) due to pipelining of transactions performed by the memory controller. This is because it takes time (latency) to open a page (activate) and close a page (precharge). You can effectively double the number of bank resources on a channel by adding a rank, but this is less beneficial than doubling the bank resource of the dram due to the fact that only one rank can communicate on the bus at any given time.

-Paul K