CPU clock cycle and instructions interpretation

computer-architecturecpuprocess

I am new in computer architecture but I know the main topics since I had it as a course before. My question is in fact little deep and related to CPU clock cycle and how processor interpret instructions when execution:

Normally, the processor executes instructions at each clock cycle. If one cycle looks like this:

 ----     
|    | 
|    | 
      ----

I want to know how this one cycle single carry the instruction bits. In other word, does CPU interprets this cycle based on raising and falling edges so raising edges represents 1's and falling edges represents 0's?

For example, if an instruction's machine code is 1001 (I know in reality it would be 64 bits or 32 bits based on the processor architecture), so we will have a single like this:

 ----                   ------
|    |                 |
|    |                 |
      ----- ----- -----

Finally, I apologize if my understanding is a bit strange but I really want to visualize the big picture of the "execution journey" inside the CPU.

Best Answer

I want to know how this one cycle single carry the instruction bits.

The wording of this question is a little hard to understand. Do you mean to ask "how does the CPU receive instructions (1001) with a single clock line"?

It doesn't. A clock signal always look like (4 cycles):

+--+  +--+  +--+  +--+
|  |  |  |  |  |  |  |
+  +--+  +--+  +--+  +--+

It's a metronome. It doesn't carry any information other than timing. It keeps all parts of the CPU working at the same speed. There are lots of connections carrying signals inside a CPU. Signals take time to change (0 -> 1 or 1 -> 0). Some change faster, some slower. Changes take place between rising edges (or falling edges depending on circuit design). The CPU will do the "next step" of the computation at every rising edge (or falling). Eg, fetch, decode, execute, could take 3 cycles. Because the rising (or falling) edges are when signals should have stabilized.

The CPU fetches instructions through other lines, like buses. Typically, the address of the next instruction is placed on the address bus, the instruction is then placed on the data bus, the CPU reads it from the data bus, decodes, executes it. The clock line is for transmitting timing information only, not "data" information.

The 2nd diagram you drew is what 1001 would look like if you were to transmit it serially, but that's a different topic.

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